Multi-Voltage Crypto Core: RTL to GDSII (Vol. 1)

32nm Multi-Voltage ASIC Design Reference

(0.95V / 0.75V Dual Supply Physical Design Methodology)

The Complete Implementation Handbook

Author: Ajay Mallesh

Reviewer: Gemini Pro 3.1 & Ajay Mallesh

Version: Version 2.0 (2026)

Date: 23/05/2026

“This project is generated with Gemini Pro 3.1 and crafted by Ajay Mallesh with ❤️.”

Technology Focus

Parameter	Specification
1. Technology Node	32nm CMOS
2. Design Type	Multi-Voltage ASIC
3. Core Type	Crypto Accelerator
4. Instance Count	~600K Instances (Pre-Synthesis)
5. Voltage Domains	0.95V / 0.75V
6. Flow Style	RTL → GDSII
7. Primary Tools	Synopsys / Cadence
8. Timing Methodology	MCMM
9. Signoff Style	PrimeTime / StarRC
10. Power Strategy	Multi-Domain Mesh PDN
11. Clocking	CTS + NDR
12. Target Audience	Physical Design Engineers / ASIC Architects

Copyright Notice:
© 2026 Ajay Mallesh. This project is open-source and released for educational and non-commercial community use. You are free to use, modify and distribute this project in accordance with the project license.
Author: Ajay Mallesh | Email: ajaymalavalli912@gmail.com | LinkedIn: www.linkedin.com/in/ajaymallesh

Legal Disclaimer

The methodologies, TCL examples, UPF constructs, synthesis flows, timing constraints and physical implementation strategies described in this document are intended exclusively for educational and research purposes.

Tool commands and flows may vary depending on: tool version, process node, foundry NDA constraints, technology LEF/DEF structure, extraction deck version, signoff correlation methodology, and EDA vendor implementation changes.

The author assumes no responsibility for: silicon failure, timing closure loss, LVS/DRC violations, power collapse, EM degradation, tape-out delay, or fabrication loss arising from improper application of the concepts described herein.

Project Introduction & Overview

Multi-Voltage Crypto Core Architecture

The crypto_top project is a high-performance ASIC cryptographic accelerator designed using 32nm CMOS technology. It contains around 30K standard cells.

Cryptographic operations such as AES-256 and SHA-3 require high-speed computation, while control logic and peripheral interfaces operate at lower speeds. To reduce power consumption and meet SoC thermal constraints, the design uses a dual-voltage architecture based on voltage scaling.

The design is divided into two voltage domains:

High-Performance Domain (0.95V / VDD): This domain contains the main datapath and computational engines. It operates at 0.95V to achieve maximum performance and timing closure using saed32rvt_ss0p95v125c.db libraries.
Low-Power Domain (0.75V / VDDL): This domain includes control logic and low-speed peripherals. Operating at 0.75V significantly reduces dynamic power consumption. It uses saed32rvt_ss0p75v125c.db libraries optimized for low power.

Physical Design Challenges

The multi-voltage architecture introduces several backend design complexities, including:

UPF-based power intent integration
Level shifters for signals crossing voltage domains
Dedicated voltage areas and power planning
MCMM timing analysis across multiple operating conditions

Tools

Synopsys Design Compiler
Synopsys ICC2

Chapter 1: Files and Directories (Linux)

1.1. Directory creations

Command: mkdir crypto_top
cd crypto_top/

1.2. Files creations

Command: gvim <file_name>, cat <file_name>, nano <file_name>

1.3. Automated Script

source setup_env.tcl
** This script will create all the required directories

Chapter 2: RTL Implementation

2.1 RTL File Implementation Logic

For a multi-voltage design, the RTL logic must be cleanly partitioned into distinct hierarchical blocks based on their target voltage. In this crypto_top design, the architecture is split into two main sections:

The High-Performance Control Block: Runs on the main 0.95V (VDD) supply. This handles the fast I/O interfaces, main state machines and clock generation.
The Low-Power Crypto Engine: Runs on the scaled 0.75V (VDDL) supply. This block performs the heavy, latency-tolerant encryption math.

The top-level Verilog file (crypto_top.v) simply acts as a wrapper that wires these two blocks together.

2.2 Level Shifters Declarations

When a signal travels from the 0.75V (VDDL) domain back to the 0.95V (VDD) domain, a Low-to-High Level Shifter is required. Without it, the 0.75V "High" signal won't fully turn off the 0.95V PMOS transistors, causing a short circuit (crowbar current).

How they are declared: In modern physical design, we do not hardcode level shifters into the RTL. The RTL just connects the wires normally. Instead, level shifters are declared and automatically inserted using the UPF (Unified Power Format) file during synthesis.

Chapter 3: Synthesis

3.1 What is Synthesis?

Synthesis is the process of translating human-readable RTL code (like Verilog) into a technology-mapped gate-level netlist. The tool reads the behavioral logic and converts it into physical logic gates (AND, OR, Flip-Flops) available in the target 32nm standard cell library, while trying to meet timing and power requirements.

3.1.1 Types of Synthesis

Logical Synthesis: Traditional synthesis that assumes zero wire delays. It only looks at the logic gates.
Physical Synthesis (Topographical): Advanced synthesis that predicts physical layout (placement and wire lengths) to give much more accurate timing and power estimates before the actual Physical Design phase.

3.2 Synthesis used in this design

For this crypto_top core, we use Physical (Topographical) Synthesis using Synopsys Design Compiler (DC). Because this is a dual-rail design, the synthesis tool must also be Multi-Voltage Aware, meaning it reads our power intent and automatically inserts the required level shifters between the 0.95V and 0.75V domains.

3.3 Files / Inputs required for Synthesis

3.3.1 RTL: The verified Verilog files (e.g., crypto_top.v, high_speed_ctrl.v, crypto_engine_lp.v) containing the design logic.
3.3.2 .lib: The logic libraries provided by the foundry. Because we have two voltage domains, we must load libraries for both the 0.95V standard cells and the 0.75V (VDDL) standard cells, usually at worst-case timing corners.
3.3.3 UPF: The IEEE 1801 Unified Power Format file. This tells the tool where the VDD and VDDL domains are and rules for inserting level shifters.
3.3.4 SDC: Synopsys Design Constraints. This file defines the clock frequencies, input/output delays and false paths.
3.3.5 Scanchains: Design for Testability (DFT) setup files. These tell the tool how to stitch the flip-flops together into long "scan chains" so the chip can be tested for manufacturing defects after fabrication.

3.4 Synthesis script file

A simplified look at the main commands inside the synthesis script:

# 1. Read the design
analyze -format verilog [./inputs/crypto_top.v]
elaborate crypto_top

# 2. Load constraints and power intent
source ./inputs/crypto_top.sdc
load_upf ./inputs/crypto_top.upf

# 3. Stitch scan chains for DFT
insert_dft

# 4. Compile the design into 32nm gates
compile_ultra -scan -timing_high_effort_script

3.5 Generated output files

3.5.1 Golden Netlist: “.v” file containing only 32nm standard cell instances and their wire connections. All abstract RTL is gone.
3.5.2 UPF: An updated “.upf” file. The tool updates the original UPF to include the exact names and locations of the level shifters it inserted.
3.5.3 Scandef: A .def file containing the scan chain trace. This ensures the PnR tool (ICC2) knows how the flip-flops are chained together and can optimize their placement.
3.5.6 SDC: The tool generates a forward-annotated SDC file. Note: It is generally not recommended to use this generated SDC for physical design.

3.6 Reports

3.6.1 report_timing: Checks the critical paths. Setup timing should be met here. Hold timing is ignored at this stage.
3.6.2 report_area: Checks the total cell count and silicon footprint.
3.6.3 report_qor: The Quality of Results report.

3.7 Sanity checks

3.7.1 check_design: Scans the netlist for logical errors (zero floating inputs, zero multi-driven nets).
3.7.2 check_mv_design: Scans the multi-voltage architecture to ensure level shifters are successfully inserted.

3.8 Automated Script for synthesis

source ./scripts/dc_compile.tcl

Chapter 4: Floorplan

4.1 creating ndm

Before physical design can begin, the tool needs a unified database containing both logical timing and physical layout information. In Synopsys ICC2, this is the New Data Model (NDM). We create the NDM by merging the synthesized .v netlist, the .db timing libraries and the physical .lef/FRAM files.

4.2 Initialize Floorplan

4.2.1 Read Netlist: The tool loads the structural netlist mapping logic to physical shapes.
4.2.2 Create Core and Die Area: We define the overall chip dimensions with a target utilization of roughly 75%.

4.3 Sanity checks

4.3.1 check_floorplan: Validates that the core area is legally defined and boundaries are closed.

Chapter 5: Port Placements

5.1 Block Pin Constraints - Placing ports

Pin constraints define exactly which edge (top, bottom, left, right) and which metal layers the ports should use, optimizing the dataflow into the high-speed control block.

5.2 Sanity checks

5.2.1 check_pin_placement: Confirms all pins are successfully dropped on the boundary.
5.2.2 check_pre_pin_placement: Verifies the pin constraint file is syntactically valid.

Chapter 6: Multi-voltage Design

6.1 UPF

We read the .upf file outputted by Synthesis into ICC2.

6.2 create voltage area

We physically draw the PD_LOW_POWER region on the floorplan canvas.

6.3 commit UPF

This tells ICC2 to finalize the power intent, mapping logical UPF definitions to the physical area and creating actual power nets (VDD and VDDL).

6.4 Sanity checks

6.4.1 check_mv_design: Validates the physical floorplan correctly supports the multi-voltage intent.
6.4.2 report_mv_cells: Generates a list of all level shifters and isolation cells.
6.4.3 report_mv_path -level_shifter -all_path: Traces wires crossing domains to guarantee level shifters sit between them.

Chapter 7: Power Delivery Network

7.1 Create Tap and bound cells

Tap Cells: Placed at regular intervals to tie the silicon substrate to ground and n-wells to power, preventing latch-up.
Boundary Cells (Endcaps): Placed at the end of every standard cell row to protect logic gates from manufacturing damage.

7.2 Sanity checks

7.2.1 check_boundary_cells: Ensures all rows are capped.

7.3 creating PG nets

We construct the power grids (VDD, VDDL and VSS). For the low-power crypto region, the VDDL mesh is generated ensuring it does not break before the inner guard band; the VDDL shapes must connect continuously edge-to-edge.

7.4 Sanity checks

7.4.1 check_pg_connectivity: Verifies the macro-level power grid is fully connected.
7.4.2 check_pg_missing_vias: Ensures vertical and horizontal power straps have vias.
7.4.3 check_pg_drc: Checks thick power metal routes for spacing/width DRC violations.

7.5 Automated script for Floorplan to PowerPlan

source ./scripts/pd_flow.tcl

Chapter 8: Congestion checks

8.1 create_placement -floorplan

Performs a fast, coarse placement of the ~30k standard cells to check how crowded the canvas gets.

8.2 congestion reports

8.2.1 report_congestion -rerun_global_router: Triggers the global routing engine to do a rough estimate of wire routing to identify "hotspots."

8.3 reset_placement

Rips up the temporary fast placement, leaving behind the clean floorplan for the actual timing-driven placement.

Chapter 9: Placement

9.1 Source ./scripts/placement.tcl

Executes global placement, legalizes cells, and performs High-Effort logic optimization to fix setup timing.

9.2 Source mcmm_setup file

Before optimization, Multi-Corner Multi-Mode (MCMM) constraints must be loaded to balance timing paths across different PVT corners.

- source ./inputs/constraints/mcmm_setup.tcl

Note: make sure to add this path properly in mcmm_setup.tcl

o source ./inputs/constraints/mcmm_corners_modes.tcl

*** Make sure all paths of mcmm & tech in “mcmm_corners_modes.tcl” are valid ***

9.3 Sanity checks

9.3.1 check_legality: Validates every standard cell is placed legally (aligned, no overlaps, voltage boundaries respected).

9.4 Reports

9.4.1 report_constraints -all_violators -max_transition: Identifies slow slew rates.
9.4.2 report_constraints -all_violators -max_capacitance: Identifies cells driving loads exceeding characterization limits.

9.5 Fixes for max trans

Upsize cells (Not Recommended manually)
Insert Buffers (Not Recommended manually before CTS)
Magnet placement: Pulls logically connected cells physically closer.
Create_bounds: Forces critical cells into a tightly restricted physical box.
Refine_placement: Gently shifts surrounding cells to legalize new constraints.
Path grouping: Assigns higher priority to failing paths.

9.6 Fixes for max cap

Upsize cells / Insert Buffers
Split load: Insert parallel buffers to halve the capacitance seen by drivers.
Cloning: Creates an exact duplicate of the struggling logic cell to share the fanout.

Chapter 10: Clock Tree Synthesis

10.1 Type of CTS used - Fish Bone

A Fishbone (or Spine) Clock Routing topology minimizes On-Chip Variation (OCV) and provides extremely low, predictable skew.

10.2 source ./scripts/cts_script.tcl

NDR Setup: Applies double-width/double-spacing rules to shield against crosstalk.
Clock Constraints: Target skews are corner-specific.
CRPR Validation: Enabled to remove artificial penalties.
Level Shifter Insertion: Exactly 2 level shifters are manually inserted before building the tree to guarantee electrical integrity and prevent massive post-tree skew destruction.
Execution Stages: Build, route, and optimize via clock_opt.

10.3 Issues / violations

Max Skew, Max Insertion Delay, Pulse Width Distortion.

10.4 & 10.5 Fixes

Fix violations via NDR usage, restricted cell lists, or manual guide buffers. Setup fails are fixed via downsizing, cloning, or Useful Skew. Hold fails are fixed purely by inserting delay buffers.

Chapter 11: Routing

11.1 source ./scripts/route.tcl

Operates in Global Routing, Track Assignment, and Detailed Routing phases.

11.2 Sanity checks & 11.3 Reports

Run check_design -checks pre_route_stage and check_routability.

11.4 Antenna Rule

Fixed via Layer Hopping or Antenna Diodes to prevent static charge blowout during manufacturing.

Chapter 12: Signoff

12.1 source ./scripts/signoff_script.tcl

StarRC: Parasitic Extraction (RC).
PrimeTime: Static Timing Analysis.
IC Validator: Physical Verification (DRC/LVS).
RedHawk/Voltus: IR Drop / EM Signoff.

Chapter 13: Advance IR drop

13.1 Introduction

Analyzes massive current surges causing the local supply voltage to sag according to Ohm’s Law ($V_{drop} = I \times R$).

13.2 Exporting the Design

# Export the physical layout
		write_def -version 5.8 -routing -all_blocks reports/crypto_top.def

		# Export the parasitic RC data
		write_parasitics -format SPEF -output reports/crypto_top.spef

13.6 Fixes for IR-Drop

Adding Decap Cells, Thickening Local Straps, and Spreading the Logic.

Chapter 14: Hard Macro Conversion

Hardening seals the internal standard cells into a single black-box component for SoC integration.

# Open routed block
		open_block crypto_top_routed

		# Create abstract view
		create_abstract -read_only

Deliverables include GDSII, LEF, Timing Models (.lib/.db), Verilog Shell, and UPF.

Appendix A: 100 General Physical Design Interview Scenarios

Section 1: Floorplanning & Power Planning

1. Scenario: You place a large memory macro right in the dead center of the core area. What happens to the design?

Answer: It acts like a giant wall. Data trying to travel from the left side of the chip to the right side must take a long detour around the macro. This creates very long wires, bad timing and routing traffic jams.

2. Scenario: You put a macro touching the absolute edge of the core boundary. What is the issue?

Answer: The router cannot access the pins on the edge side of the macro. You must leave a small gap between the macro and the core boundary for wires to travel through.

3. Scenario: You forgot to add Tap cells to your floorplan. What will happen when the chip turns on?

Answer: Tap cells connect the base of the silicon to power and ground. Without them, a sudden voltage spike will create a short-circuit inside the silicon (called Latch-up), which permanently burns the chip.

4. Scenario: You decided to use huge, thick metal straps for the entire power grid to make sure there is no voltage drop. What is the negative side effect?

Answer: Power straps take up metal routing tracks. If you use too much metal for power, there won’t be enough empty space left for the router to connect the actual signal wires, leading to a blocked design.

5. Scenario: You did not put enough power straps. What happens?

Answer: The resistance of the power grid goes up. When many cells turn on at once, the voltage drops (IR Drop). If the cells don't get full voltage, they switch slowly and timing fails.

6. Scenario: Why do we put Endcap (Boundary) cells at the end of every standard cell row?

Answer: During manufacturing, the edges of the cell rows can get damaged or stressed. Endcap cells are "dummy" cells with no logic inside. They sit on the edges to take the damage and protect the real logic gates inside the row.

7. Scenario: You placed all your high-speed, power-hungry macros in the top-right corner of the chip. Why is this bad?

Answer: This creates a "thermal hotspot." All the heat is trapped in one small area, which can slow down the transistors or physically damage the chip. Macros should be spread out evenly if possible.

8. Scenario: What happens if you do not add a routing blockage over a hard macro?

Answer: The tool might try to route standard signal wires straight over the macro and drop vias into it. This will short-circuit the internal wiring of the macro.

9. Scenario: The input ports (pins) are placed on the top of the chip, but the logic they connect to is placed at the bottom. What is the result?

Answer: The tool has to draw a massive wire across the whole chip. This creates huge wire delay and setup timing violations right from the start.

10. Scenario: You forgot to connect VSS (Ground) to a macro block. What happens?

Answer: The macro will not turn on. Electricity needs a complete circle (from Power to Ground) to flow.

Section 2: Placement & Congestion

11. Scenario: The tool placed 50,000 cells in one tiny corner of the chip. What is this called and why is it bad?

Answer: This is called local congestion. The router will fail because there are not enough metal tracks in that tiny area to connect all those cells.

12. Scenario: How do you fix a heavily congested spot in placement?

Answer: You use "Placement Blockages" or "Cell Padding" (adding invisible empty space around cells). This forces the tool to spread the cells out into wider areas.

13. Scenario: A wire is too long, causing the signal to travel very slowly. The tool reports a "Max Transition" violation. How do you fix it?

Answer: You can cut the long wire in half by inserting a buffer in the middle. You can also upsize the driving cell so it pushes the signal harder.

14. Scenario: One small cell is trying to drive 100 other cells. The tool reports a "Max Capacitance" violation. How do you fix it?

Answer: You can "clone" the driver. You make an exact copy of the driving cell and let the first cell drive 50 and the cloned cell drive the other 50.

15. Scenario: Two cells that talk directly to each other are placed very far apart by the tool. How do you force them together?

Answer: You can use "Bounds" to lock them into the same small box, or define them as a "Magnet" so they pull towards each other.

16. Scenario: Your standard cell utilization is 90% right after placement. Is this good?

Answer: No, it is too high. The tool needs empty space to add buffers during clock building and routing. If you start at 90%, the chip will be completely full and fail later. Target 70-75% to start.

17. Scenario: You fix all your timing violations by replacing small cells with huge, high-drive cells. What is the negative side effect?

Answer: High-drive cells take up more physical space (causing congestion) and they leak much more power.

18. Scenario: Why is it bad if the tool places flip-flops perfectly in a straight line?

Answer: If they are in a straight line, they will all draw power from the exact same local power strap at the exact same time when the clock hits. This creates a massive localized voltage drop.

19. Scenario: You have a Max Transition violation, but you cannot insert a buffer because there is no physical space left. What else can you do?

Answer: Change the driving cell to a Low-VT (LVT) cell. LVT cells switch much faster without needing to be physically bigger.

20. Scenario: What is Scan Reordering and why do we do it during placement?

Answer: Scan chains connect all flip-flops for testing. If connected in random order, the wires will cross back and forth across the chip, causing huge congestion. Reordering connects them based on their physical placement, keeping the wires short.

Section 3: Clock Tree Synthesis (CTS)

21. Scenario: The clock takes 5ns to travel from the clock port to the flip-flops. This is called High Insertion Delay. Why is it bad?

Answer: The longer the clock travels through buffers, the more sensitive it is to temperature and voltage changes on the chip. This makes timing very unpredictable.

22. Scenario: The clock reaches Flop A at 1ns, but reaches Flop B at 2ns. What is this called and what does it cause?

Answer: This is called Clock Skew. It is very dangerous because it can cause Hold timing violations (data races past the clock).

23. Scenario: Why do we use "Double Spacing" rules when routing clock nets?

Answer: Clocks toggle constantly. If a data wire is routed too close, the clock will create noise (crosstalk) on the data wire. Double spacing keeps them safely apart.

24. Scenario: Why do we use special "Clock Buffers" instead of normal "Logic Buffers" to build the tree?

Answer: Normal buffers might have a fast rise time but a slow fall time. Clock buffers are built to be perfectly symmetrical, so the clock wave stays perfectly square as it travels.

25. Scenario: The router put the main clock wires on Metal 1 and Metal 2. Why is this a mistake?

Answer: Lower metals are very thin and have high resistance. The clock is the most important signal; it must be routed on thick, upper metals (like M5 or M6) to travel fast.

26. Scenario: What does an ICG (Integrated Clock Gating) cell do?

Answer: It acts like an on/off switch for the clock. If a block of logic is not being used, the ICG shuts off the clock to that block to save power.

27. Scenario: An ICG cell is placed very far away from the flip-flops it controls. What is the risk?

Answer: The "enable" signal telling the clock to turn on might arrive too late, missing the clock edge entirely.

28. Scenario: Why do we wait until after CTS to fix Hold violations?

Answer: Hold timing depends entirely on when the clock arrives. Before CTS, the clock is "ideal" (fake zero delay). If you add buffers to fix Hold early, you will be fixing fake numbers and wasting space.

29. Scenario: What is "Useful Skew"?

Answer: It is a trick to fix Setup timing. If data is arriving late to a flip-flop, you intentionally delay the clock going to that flop. This gives the data extra time to get there.

30. Scenario: You used Useful Skew to delay the clock to Flop B. But Flop B sends data to Flop C. What is the new problem?

Answer: Because Flop B's clock is now late, it launches its data late. This might create a new Setup violation at Flop C.

Section 4: Routing & Design Rule Checks (DRC)

31. Scenario: What is an Antenna Violation?

Answer: During manufacturing, metal is etched using plasma. Long metal wires act like antennas and collect static electricity. If the wire connects to a sensitive transistor gate, the spark will burn the gate and destroy it.

32. Scenario: How does the router fix an Antenna Violation?

Answer: It uses "Layer Hopping" (breaking the wire and jumping to a higher metal layer to stop the charge from building up) or it inserts an "Antenna Diode" to safely drain the electricity into the ground.

33. Scenario: Two wires are routed perfectly parallel and very close together for a long distance. What happens?

Answer: They act like a capacitor. If one wire switches, it can slow down or speed up the signal on the other wire. This is called Crosstalk Delay.

34. Scenario: How do you fix Crosstalk Delay?

Answer: Move the wires further apart (increase spacing), upsize the driver to overpower the noise, or put a grounded metal wire between them to act as a shield.

35. Scenario: The router leaves an "Open Net" (a wire that didn't connect). Why does this happen?

Answer: The destination pin might be blocked by other wires, or the routing channel is 100% full and there are no empty tracks left to use.

36. Scenario: Why do we force horizontal routing on Metal 3 and vertical routing on Metal 4?

Answer: This is called preferred routing direction. It creates a grid. If we allowed wires to go any direction on any layer, they would block each other constantly and cause massive congestion.

37. Scenario: A single via is connecting a very important, high-current wire. What is the risk?

Answer: Vias have high resistance. A single via might fail or melt. High-current wires should use "Double Vias" (two vias side-by-side) for safety.

38. Scenario: What is Electromigration (EM)?

Answer: When too much current flows through a thin wire for a long time, the electricity literally pushes the metal atoms out of place. Eventually, the wire breaks or shorts out.

39. Scenario: How do you fix an EM violation?

Answer: Make the metal wire wider, or route the signal using multiple metal layers at the same time to spread the current out.

40. Scenario: The tool reports a "Short" violation. What does this mean?

Answer: Two completely different signals were routed so close together that their metal shapes are physically touching. This ruins both signals.

Section 5: Timing Closure

41. Scenario: A path has a Setup violation. What is the fastest way to fix it without touching the wire?

Answer: Swap the cells on the path from High-VT (HVT) or Regular-VT (RVT) to Low-VT (LVT). LVT cells process data much faster.

42. Scenario: If LVT cells are so fast, why don't we build the whole chip out of them?

Answer: LVT cells have massive "leakage power." They waste a lot of electricity even when the chip is just sitting idle doing nothing.

43. Scenario: A path has a Hold violation (data is moving too fast and racing past the clock). How do you fix it?

Answer: You insert delay buffers into the data path. This acts like a speed bump, slowing the data down so it arrives safely after the clock edge.

44. Scenario: Why does adding buffers fix Hold, but not break the clock?

Answer: Because you are adding the buffers to the data wire, not the clock wire.

45. Scenario: A single path has both a Setup violation AND a Hold violation at the same time. Which one do you fix first?

Answer: Always fix Setup first. You fix Setup by making the path faster. Then, you fix Hold by adding a delay buffer at the very end of the path where it won't hurt the Setup time you just fixed.

46. Scenario: What is a False Path?

Answer: It is a physical wire connection that exists, but data never actually travels through it during normal operation (like a reset signal that only happens once). We tell the tool to ignore it so it doesn't waste time trying to optimize it.

47. Scenario: What is a Multi-Cycle Path?

Answer: Some calculations are too big to finish in one clock cycle. We tell the tool "Multi-Cycle Path 2", which means the data is allowed to take two full clock pulses to reach the end.

48. Scenario: Setup timing is failing mostly at the "Slow" temperature corner (like 125°C). Why does heat cause Setup failures?

Answer: Heat increases the resistance in the silicon and metal. High resistance means signals travel slower, causing them to arrive late (Setup failure).

49. Scenario: Hold timing is failing mostly at the "Fast" temperature corner (like -40°C). Why does cold cause Hold failures?

Answer: Cold temperatures make transistors switch incredibly fast. The data finishes processing so quickly that it crashes into the next flip-flop before the clock is ready (Hold failure).

50. Scenario: Your Setup margin is exactly 0.00ns (perfectly met). You have a Hold violation. If you add a delay buffer to fix Hold, it will slow the path down and cause a Setup violation. What is a smart fix?

Answer: Instead of adding a new buffer, look at the driving cell. If you downsize the driving cell slightly, it will drive the signal a tiny bit slower. This might fix the Hold violation without adding enough delay to break the Setup timing.

Section 6: Advanced Timing & On-Chip Variation (STA)

51. Scenario: A single path has a massive Setup violation. You check the layout and the physical wire is extremely short. How is a Setup violation even possible on a short wire?

Answer: Setup depends on total delay, not just wire length. If the wire is short, the delay is coming from the cells. The driving cell likely has a massive fanout (trying to drive 50 other gates) or is heavily under-sized.

52. Scenario: The tool reports a Hold violation on a path. You look at the clock tree and realize the launch flip-flop and capture flip-flop share the exact same clock wire for 90% of their journey. Why is the tool penalizing you for clock skew?

Answer: You forgot to enable CRPR (Clock Reconvergence Pessimism Removal). Because of On-Chip Variation (OCV), the timing engine assumes the worst case: it artificially slows down the launch clock and speeds up the capture clock. CRPR tells the tool, "Hey, this is the exact same physical wire, it can't be fast and slow at the same time," and removes the fake penalty.

53. Scenario: Why does temperature inversion happen at advanced nodes (like 16nm and below)? Why does the chip sometimes get slower at -40°C?

Answer: In older nodes, cold temperatures always meant less resistance and faster transistors. However, at modern nodes, the threshold voltage ($V_{th}$) of the transistor is highly sensitive. At cold temperatures, $V_{th}$ increases. If you are running the chip at a very low supply voltage (like 0.75V), that higher $V_{th}$ chokes the transistor, drastically reducing the drive current ($I_{ds}$) and slowing the cell down.

54. Scenario: You have a Setup margin of exactly 0.00ns. You discover a Hold violation of 2ns on the exact same path. Can you fix this by just adding delay buffers?

Answer: No. If you add 2ns of delay buffers to fix Hold, you will instantly create a 2ns Setup violation, bouncing back and forth forever. This means your clock skew is fundamentally broken. You must fix this architecturally by pulling the clock back on the capture flop (Useful Skew) or fixing the clock tree design.

55. Scenario: You have a data signal crossing from a 500MHz clock domain to a completely asynchronous 100MHz clock domain. PrimeTime reports a Setup violation. How do you fix the timing?

Answer: You don't. This is a trick question. Asynchronous domains have clocks that drift constantly relative to each other; they will always violate setup/hold eventually. You must declare this a False Path in STA and use a structural synchronizer (like a 2-stage flip-flop synchronizer or a FIFO) in the RTL to handle the data safely.

56. Scenario: What is "Time Borrowing" and which component allows it?

Answer: Flip-flops have a hard edge; data must arrive before the clock hits. Latches are transparent for half the clock cycle. If data arrives a little late to a latch, it doesn't fail; it just flows through and "borrows" time from the next logic stage. This is highly useful for smoothing out uneven logic paths.

57. Scenario: You see a Timing Path where the Required Time is earlier than the Launch Time. What does this mean?

Answer: This is a Half-Cycle Path. The launch flop is triggered on the rising edge of the clock, but the capture flop is triggered on the falling edge. The data only has half a clock cycle to arrive, cutting your timing margin in half.

58. Scenario: Why do we derate the launch path "late" (slower) for Setup analysis, but "early" (faster) for Hold analysis?

Answer: STA must always prove the absolute worst-case scenario. For Setup, the worst case is if the data launches extremely late and struggles to reach the end. For Hold, the worst case is if the data launches extremely early and races past the clock too fast.

59. Scenario: Why is "Useful Skew" dangerous in a design with very high On-Chip Variation (OCV)?

Answer: Useful Skew intentionally misaligns the clock to give data more time. However, OCV means clock delays shift randomly due to manufacturing differences. If you intentionally push the clock to the absolute edge to fix timing, a slight OCV shift in the real silicon will instantly push it over the edge and break the chip.

60. Scenario: You have a Setup violation on a path. You swap the driving cell for an Ultra-High Drive cell to push the signal faster. The Setup violation gets worse. Why?

Answer: Ultra-High Drive cells are physically massive. They have a huge input capacitance (pin load). By upgrading the cell, you sped up the current net, but you severely overloaded the previous cell driving it, creating a worse delay upstream.

Section 7: Advanced Clock Tree Synthesis (CTS)

61. Scenario: Should a Clock Gating Cell (ICG) be placed closer to the main Clock Root, or closer to the Flip-Flops it controls?

Answer: It must be placed closer to the Flip-Flops. The entire point of an ICG is to save power by turning off the clock wire. If you place it near the root, you save power on the whole branch. However, the "Enable" signal driving the ICG usually comes from local logic. If the ICG is far away, the Enable signal will arrive late, missing the clock edge and causing a glitch.

62. Scenario: Why do some high-performance chips (like CPUs and Crypto Cores) use a "Clock Mesh" instead of a "Clock Tree"?

Answer: A tree branches out, meaning the end points can have high skew due to OCV. A Clock Mesh literally shorts all the final clock branches together into a giant metal grid across the chip. This guarantees near-zero skew everywhere and extreme stability, but it burns a massive amount of dynamic power.

63. Scenario: You built a clock tree with perfect 0.00ns skew between all flops. However, the Insertion Delay (latency from root to flop) is a massive 8ns. Is this a good clock tree?

Answer: No, it is terrible. A massive insertion delay means the clock passes through dozens of buffers. Because of OCV, every buffer adds a percentage of random delay variation. An 8ns deep tree will have wild, unpredictable skew in actual physical silicon due to temperature and voltage fluctuations.

64. Scenario: Does Global Skew matter more, or does Local Skew matter more?

Answer: Local Skew matters much more. If Flop A and Flop Z are on opposite sides of the chip and never talk to each other, it doesn't matter if their clocks are skewed by 1ns. But if Flop A talks directly to Flop B (local), even a 0.1ns skew can cause a fatal Hold violation.

65. Scenario: What is the difference between Clock Skew and Clock Jitter?

Answer: Skew is spatial (physical). It is the difference in arrival time between two different physical locations on the chip. Jitter is temporal (time). It is the fluctuation of the clock period at the same location from cycle to cycle, caused by the PLL (Phase Locked Loop) or power supply noise.

66. Scenario: Why do some designers prefer building clock trees entirely out of Clock Inverters instead of Clock Buffers?

Answer: A buffer is just two inverters internally. It is difficult to make a PMOS and NMOS exactly equal, so buffers often have unequal rise and fall times, degrading the clock pulse width. By using single inverters, every rising edge becomes a falling edge at the next stage, naturally canceling out the rise/fall asymmetry.

67. Scenario: You applied "Double Spacing" to your clock nets to prevent crosstalk. At what physical point must you drop the rule and return to normal spacing?

Answer: You must drop the rule right before the leaf level (the pins of the flip-flops). Flip-flop pins are packed tightly at the standard cell level. If you force double-spacing all the way into the pin, the router will fail to connect them because there isn't enough physical room.

68. Scenario: You run CTS. Afterward, your Hold violations explode from 0 to 5,000. Why did CTS cause this?

Answer: Before CTS, the clock arrived at exactly 0.00ns for every flop (ideal clock). CTS builds real wires, introducing Clock Skew. If the clock arrives at the capture flop even a fraction of a nanosecond before the launch flop, the data easily races past the clock, causing thousands of hold failures.

69. Scenario: You route a shield wire next to a critical clock net to block crosstalk. Should you connect the shield to VDD (Power) or VSS (Ground)?

Answer: Always VSS (Ground). VSS is the universal quiet reference point. VDD is full of dynamic voltage drops and switching noise. Shielding with VDD would inject power noise directly into your clock line.

70. Scenario: How do you fix a Max Transition violation on a High-Fanout Reset net?

Answer: You cannot just upsize the driver because driving 10,000 flops will overload any cell. You must build a "Reset Tree" (just like a clock tree) by cloning buffers and distributing the load symmetrically.

Section 8: Multi-Voltage, UPF, & Power Intent

71. Scenario: A standard cell in a 0.0V (Shut Down) domain sends a signal to a cell in a 1.0V (Always On) domain. You forgot to add an Isolation Cell. What happens?

Answer: When the first domain shuts down, its output floats (it becomes neither 1 nor 0, but an unpredictable middle voltage). The receiving cell in the 1.0V domain sees this floating input, which partially turns on both its NMOS and PMOS transistors. This creates a direct short to ground (Crowbar Current), burning out the 1.0V domain.

72. Scenario: A signal goes from a 0.75V domain to a 0.95V domain. Where exactly must the Low-to-High Level Shifter be physically placed?

Answer: It must be placed inside the 0.95V domain. A Level Shifter needs access to the higher voltage supply (0.95V) to pull the signal up to the new level. If placed in the 0.75V domain, it wouldn't have access to the required high-voltage rail.

73. Scenario: What is a Retention Flip-Flop?

Answer: When a power domain is shut off to save battery, all flip-flops lose their memory. A Retention Flop contains a tiny "balloon" latch that runs on a separate, always-on backup power supply. Before shut-off, it saves the data and when power returns, it restores the state immediately without needing a full system reboot.

74. Scenario: You placed an Always-On (AON) buffer inside a domain that turns completely off. How does it stay alive?

Answer: AON cells require a secondary, continuous power pin (often called VDD_Backup). The router must physically draw a special power wire through the shutdown domain just to feed this specific cell.

75. Scenario: Domain A and Domain B both operate at exactly 0.95V. However, Domain A is controlled by Power Switch A and Domain B is controlled by Power Switch B. Do you need Level Shifters? Do you need Isolation Cells?

Answer: You do not need Level Shifters because the voltages are identical. However, you absolutely need Isolation Cells. Since they have different switches, Domain A could be turned off while Domain B is awake, creating the floating-input crowbar issue.

76. Scenario: What is the difference between Static IR-Drop and Dynamic IR-Drop?

Answer: Static IR-Drop assumes the chip is sitting idle and calculates voltage drop based on constant leakage current. Dynamic IR-Drop uses a real switching simulation (VCD file) to calculate the massive voltage spikes caused when thousands of flip-flops toggle at the exact same nanosecond.

77. Scenario: You have empty space in the corner of your floorplan. Should you fill it with Decoupling Capacitors (Decaps) to help your power grid?

Answer: No. Decaps act as local batteries that supply instantaneous current during switching. If they are placed far away in an empty corner, the resistance of the wire connecting them to the active logic defeats their purpose. Decaps must be placed as close to the switching hotspots as possible.

78. Scenario: What is "Inrush Current" and how do Power Switches manage it?

Answer: When a sleeping power domain is suddenly turned back on, all the empty wires and cells instantly suck a massive amount of power to charge up. This "inrush" can steal power from the rest of the chip, causing a brownout. Power switches are "daisy-chained" (turned on one by one in a delayed sequence) to slowly charge the domain and prevent grid collapse.

79. Scenario: Why does a slow transition (bad slew rate) cause high dynamic power consumption?

Answer: Every CMOS gate has a threshold where it flips from 0 to 1. During that exact middle moment, both the NMOS and PMOS are slightly open, causing a temporary short-circuit current. If the signal transition is very slow, the gate spends more time in that "middle state," burning excess short-circuit power.

80. Scenario: You are sizing an MTCMOS Power Switch (Header switch). What is the danger of making it too big? What is the danger of making it too small?

Answer: If the switch is too small, its resistance is too high, causing massive IR-drop across the switch when the block is running. If it is too big, the switch itself will have massive leakage power when turned off, defeating the purpose of shutting the block down in the first place.

Section 9: Advanced Routing & Physical Verification

81. Scenario: Your standard cell utilization is only 40% (plenty of empty space), but the router is failing with massive congestion. Why?

Answer: You likely used high pin-density standard cells or you placed macros in a way that formed a narrow "bottleneck" channel. Even with 60% empty space, if all wires are forced through a tiny physical corridor, the metal tracks will overflow.

82. Scenario: An input pin of a logic gate must be permanently tied to logic "1". Why do we use a "Tie-High Cell" instead of just wiring the pin directly to the VDD power rail?

Answer: Connecting the thin gate oxide of a transistor directly to the thick, noisy VDD rail makes it highly vulnerable to ESD and voltage spikes, which will blow the gate. A Tie-High cell contains a resistor-like internal structure to safely deliver the logic "1" without the electrical risk.

83. Scenario: What is the exact difference between a Placement "Fence" and a "Region"?

Answer: A Fence is an exclusive hard constraint: specified cells MUST go inside and no other cells are allowed in. A Region is inclusive: specified cells MUST go inside, but if there is leftover room, the tool is allowed to place other random cells in there too.

84. Scenario: Net A and Net B are routed side-by-side. Net A is totally quiet (static 0). Net B suddenly switches from 0 to 1. Because of crosstalk capacitance, Net A experiences a "Glitch" and spikes up to 0.4V. Will the chip fail?

Answer: It only fails if 0.4V crosses the threshold voltage of the receiving gate. If the receiver interprets 0.4V as logic "1", it will register a false data point. If the receiving cell has a high threshold (e.g., 0.5V), it will ignore the 0.4V glitch and the chip will survive.

85. Scenario: What is the difference between Crosstalk Glitch and Crosstalk Delay?

Answer: Glitch happens when the victim net is sitting perfectly still and the aggressor causes it to bounce. Delay happens when both nets are switching at the exact same time. If they switch in opposite directions, they fight each other and slow the signal down.

86. Scenario: What is the difference between a Placement HALO and a Routing Blockage?

Answer: A HALO is drawn around a macro; it stops the tool from placing any standard cells too close to the macro's edge. A Routing Blockage stops the tool from drawing metal wires across that specific area.

87. Scenario: The router inserts an Antenna Diode to fix an antenna violation on a long wire. Should the diode be placed near the driving cell, or near the receiving cell?

Answer: Near the receiving cell. The danger of the antenna effect is the static charge blowing out the delicate gate oxide of the receiving transistor. The diode must be as close to that gate as possible to siphon off the charge.

88. Scenario: What exactly happens during the "Track Assignment" phase of routing?

Answer: Global Routing divides the chip into grids and plans the rough path. Track Assignment is the middle step: it looks at the rough path and assigns the wire to a specific, continuous physical metal track before detailed routing finishes the exact connections.

89. Scenario: Your wires are perfectly connected using single vias. The tool goes back and spends hours swapping them to "Redundant Vias" (double vias). Why waste the space?

Answer: Vias are microscopic holes filled with metal. During manufacturing, a single via can fail. A second via provides redundancy and improves yield.

90. Scenario: At advanced nodes (7nm/5nm), standard cells are so small that the router cannot physically drop vias to connect to their pins. How is this solved?

Answer: The foundry provides a predefined "Pin Access" pattern. Placement must align to a strict grid so vias can legally land on allowed access points.

Section 10: Signoff, Parasitics & Verification

91. Scenario: Your design passes STA but fails silicon.

Answer: IR drop or real silicon voltage variation was not modeled.

92. Scenario: LVS soft error.

Answer: Electrical connection through substrate or unintended path.

93. Scenario: Minimum metal area violation.

Answer: Tiny metal can be removed during CMP process.

94. Scenario: EM difference in power vs signal nets.

Answer: Power nets carry DC stress, signals alternate direction.

95. Scenario: RC worst corner for setup check.

Answer: Maximum resistance causes worst delay.

96. Scenario: Base DRC vs Metal DRC.

Answer: Base = silicon rules, Metal = routing layers rules.

97. Scenario: Metal fill insertion.

Answer: Ensures uniform density for CMP polishing.

98. Scenario: IR drop causing hold violation.

Answer: Clock skew shifts timing unexpectedly.

99. Scenario: Metal fill affecting timing.

Answer: Adds parasitic capacitance, increasing delay.

100. Scenario: Setup-hold ECO loop.

Answer: Fix using LVT swap, downsizing, or skew adjustment.