Multi-Voltage Crypto Core

RTL - Multi-Voltage Crypto Core

Designed a 128-bit cryptographic accelerator using a multi-voltage architecture to optimize both power consumption and performance in ASIC-based systems. The design separates functionality into a 0.75V low-power domain for key generation and a 0.95V high-performance domain for encryption processing, demonstrating practical power-aware digital design techniques.

Architecture Overview

The low-power block generates a pseudo-random keystream using a 128-bit LFSR-based key scheduler, while the high-performance encryption engine implements a 64-round Substitution-Permutation Network (SPN) architecture. A dedicated voltage-domain interface safely transfers key data between domains, reflecting real-world ASIC design practices for power-domain integration.

Key Features

• 128-bit encryption datapath with configurable architecture
• Low-power key generation operating at 0.75V
• High-performance cipher core operating at 0.95V
• Safe voltage-domain crossing through interface registers
• 64-round SPN-based encryption engine
• Parallel 4-bit S-Box implementation for non-linear transformations
• Deep pipelining for improved throughput and timing performance
• Fully synthesizable and modular Verilog RTL

Applications

Secure SoCs, IoT security accelerators, embedded cryptographic engines, hardware security modules (HSMs), and power-constrained ASIC designs.

Skills Demonstrated

• Verilog RTL Design
• Multi-Voltage Design
• Cryptographic Hardware Architecture
• ASIC Design Methodology
• Power-Aware Digital Design
• Pipelined Datapath Design
• Parameterized Hardware Development

UPF - Multi-Voltage Power Intent Design

Developed a silicon-ready Unified Power Format (UPF) specification for a multi-voltage cryptographic accelerator, enabling power-aware implementation and verification across multiple voltage domains. The power architecture partitions the design into a 0.95V high-performance domain and a 0.75V low-power domain, optimizing overall power consumption while maintaining system functionality and reliability.

Power Intent Architecture

The UPF defines dedicated power domains, supply ports, supply nets, and domain-specific power connections to accurately capture the design's power intent. Voltage states and a Power State Table (PST) were created to model valid operating modes, ensuring correct behavior during power-aware simulation and implementation. Level shifter strategies were also specified to safely manage signal transfers between voltage domains, addressing voltage compatibility requirements during physical design.

Key Features

• Defined separate power domains for high-performance and low-power functional blocks
• Created supply ports, supply nets, and primary power/ground connections
• Configured voltage operating states for 0.95V and 0.75V domains
• Developed Power State Tables (PST) to represent valid system power modes
• Specified low-to-high and high-to-low level shifter insertion strategies
• Enabled power-aware simulation, synthesis, place-and-route, and signoff flows
• Designed according to industry-standard low-power ASIC methodologies
• Supported seamless integration between RTL, UPF, and physical design implementation

Applications

Low-power ASICs, secure cryptographic accelerators, IoT SoCs, edge computing devices, battery-powered systems, and advanced multi-voltage semiconductor designs.

Skills Demonstrated

• UPF (Unified Power Format)
• Low-Power Design Techniques
• Multi-Voltage Architecture
• Power Domain Management
• Level Shifter Implementation
• Power State Table (PST) Development
• Power-Aware Verification
• ASIC Physical Design Methodology
• SoC Power Intent Specification

Key Achievement

Successfully defined and implemented a complete UPF-based power intent for a multi-voltage cryptographic accelerator, enabling safe cross-domain communication, power-aware verification, and silicon-ready low-power ASIC implementation.

SDC - Synthesis Timing Constraints

SDC for Synthesis (Only)

Developed a synthesis-focused Synopsys Design Constraints (SDC) file for a multi-voltage cryptographic accelerator, defining the timing and design-rule requirements required for logic synthesis and optimization. The constraint set establishes clock definitions, I/O timing budgets, transition limits, fanout restrictions, and load assumptions to guide synthesis tools toward achieving timing closure and producing an optimized gate-level netlist.

Synthesis Constraint Features

• Defined primary clock and virtual clock constraints
• Applied input and output delay budgets for timing-driven synthesis
• Configured maximum fanout and transition limits for signal integrity
• Specified output load and input transition characteristics
• Enabled timing optimization and synthesis-driven design rule checking
• Generated synthesis-ready constraints for gate-level netlist creation
• Separated synthesis constraints from physical design timing signoff requirements

Synthesis Constraints Details

The SDC includes a 500 MHz system clock (2 ns period), input/output delay constraints, maximum fanout limits, transition constraints, and load modeling to accurately represent the intended operating environment during synthesis. These constraints enable efficient logic optimization, buffer insertion, gate sizing, and timing-driven synthesis while maintaining design quality and performance targets.

Applications

ASIC synthesis flows, timing-driven logic optimization, cryptographic accelerators, high-performance digital systems, and multi-voltage SoC development.

Skills Demonstrated

• SDC Development
• Timing Constraint Creation
• Logic Synthesis
• Static Timing Analysis Fundamentals
• Clock Definition
• I/O Timing Budgeting
• Design Rule Constraints
• Timing Closure Methodology
• ASIC Front-End Design Flow

Key Achievement

Created a comprehensive synthesis constraint environment that enables timing-driven optimization and supports successful gate-level implementation of a high-performance multi-voltage cryptographic accelerator.

MCMM - Physical Design Timing Constraints

Multi-Corner Multi-Mode Timing Setup

Developed a complete Multi-Corner Multi-Mode (MCMM) timing constraint environment for the physical design implementation of a multi-voltage cryptographic accelerator. Created corner-specific, mode-specific, and scenario-specific TCL constraint files to support timing analysis, optimization, and signoff across multiple operating conditions.

MCMM Configuration

The MCMM setup includes Fast-Fast (-40°C) and Slow-Slow (125°C) process corners, covering both Functional and Scan/Test operating modes. A centralized MCMM setup script was used to define analysis views and manage scenario configurations for place-and-route and timing closure.

MCMM Key Features

• Created corner-specific timing constraints for FF (-40°C) and SS (125°C) conditions
• Developed separate Functional and Scan mode constraint files
• Defined setup analysis scenarios across multiple PVT conditions
• Configured MCMM views for timing optimization and signoff
• Enabled robust setup timing analysis across worst-case and best-case conditions
• Supported physical design stages including placement, CTS, routing, and STA
• Improved timing closure coverage by validating design across multiple operating scenarios

MCMM Files Developed

Corner Constraints:

• crypto_c_ff_m40c.tcl
• crypto_c_ss_125c.tcl

Mode Constraints:

• crypto_m_func.tcl
• crypto_m_scan.tcl

Scenario Constraints:

• crypto_s_func_ff_m40c.tcl
• crypto_s_func_ss_125c.tcl
• crypto_s_scan_ff_m40c.tcl
• crypto_s_scan_ss_125c.tcl

MCMM Setup:

• mcmm_crypto_setup.tcl

MCMM Skills Demonstrated

• MCMM Setup
• Physical Design Constraints
• Static Timing Analysis (STA)
• Timing Closure
• PVT Corner Analysis
• Functional & Scan Timing
• Innovus/ICC2 Constraint Management
• Signoff Methodology
• ASIC Physical Design Flow

Key Achievement

Built a complete MCMM timing environment enabling accurate timing analysis and optimization across multiple process, voltage, temperature, and operating-mode scenarios, supporting successful physical design implementation and signoff readiness.

Synthesis Script - Multi-Voltage Design

Developed a complete Synopsys Design Compiler (dc_shell) synthesis flow for a 2-domain multi-voltage cryptographic accelerator (0.95V / 0.75V). The script integrates RTL compilation, UPF-based power intent, multi-voltage handling, DFT insertion, and final netlist export in a single automated flow.

Flow Architecture

The flow is structured to ensure correct execution order for multi-voltage synthesis → level-shifter insertion → scan insertion → final signoff data generation, making it suitable for silicon-ready ASIC implementation.

Key Flow Features

• Configured multi-voltage libraries including core, ultra-low-voltage, and level-shifter cells
• Integrated UPF power intent to define 0.95V and 0.75V domains
• Applied synthesis constraints (SDC) for timing-driven optimization
• Enabled multi-voltage checks and fixes (MV DRC, level shifters, tie cells)
• Automated compile → MV fix → incremental optimization flow
• Inserted DFT scan chains with scan enable, scan-in, scan-out, scan clock/reset handling
• Controlled scan architecture (single-chain configuration for simplicity)
• Ensured proper naming, consistency, and synchronization across outputs

Flow Stages

1. Setup & Library Configuration

Defines technology libraries including standard cell libraries (0.95V / 125°C), low-voltage libraries (0.75V), and level shifter libraries for voltage crossing.

2. RTL & Power Intent Integration

• RTL elaboration of crypto_top
• UPF loaded for multi-voltage domain definition
• Voltage assignments applied to power nets (0.95V / 0.75V / GND)

3. Timing Constraints

• SDC file read for synthesis timing requirements
• Operating conditions set for worst-case analysis
• Multi-voltage design check enabled

4. Multi-Voltage Optimization

• Fixes for tie cells and ideal net handling
• Automatic level-shifter insertion enabled
• Multi-voltage design rule fixes applied before compilation

5. Logic Synthesis

• compile_ultra -scan for optimized and scan-ready netlist
• Retiming and clock gating enabled
• Incremental compile after MV cell insertion

6. DFT Insertion

• Scan ports created (scan enable, scan-in, scan-out)
• Scan architecture defined and validated
• DFT protocol generated and inserted into netlist
• Single scan chain configured for simplicity

7. Output Generation

Exports silicon-ready deliverables:

• Gate-level Verilog netlist
• Synthesized SDC
• UPF (updated with naming consistency fixes)
• ScanDEF for backend physical design tools

Skills Demonstrated

• Synopsys Design Compiler
• Multi-Voltage Synthesis
• UPF Integration
• DFT Insertion
• Scan Chain Design
• Level Shifter Handling
• Timing-Driven Synthesis
• ASIC Flow Automation
• Physical Design Readiness

Key Achievement

Built a fully automated multi-voltage synthesis and DFT flow that integrates power intent, timing constraints, and scan insertion, producing a silicon-ready netlist for a 2-domain cryptographic accelerator with correct voltage handling and testability support.

Floorplan-to-Powerplan Flow

Developed a full physical design initialization flow for a multi-voltage cryptographic SoC, covering library setup, floorplanning, pin placement, power intent integration, and early physical readiness for placement and routing.

Design Methodology

The flow is built using Synopsys ICC2-style block implementation methodology, ensuring proper coordination between RTL netlist, UPF power intent, and physical constraints.

Key Features

• Created a design library environment (NDM) using multiple technology variants (HVT/LVT/RVT/SRAM/tech files)
• Imported and linked synthesized gate-level netlist
• Initialized core-aware floorplan with 70% utilization for routing flexibility
• Performed structured I/O pin placement with layer and spacing constraints
• Integrated multi-voltage UPF into physical design and committed power intent
• Defined voltage-aware design regions (voltage areas) for domain separation
• Enabled multi-voltage design rule checking (MV DRC)
• Prepared design for macro integration, power planning, and routing closure

Flow Breakdown

1. Design Setup & Library Initialization

• Created design library (CRYPTO_TOP_SCANCHAIN.nlib)
• Loaded technology and standard cell libraries (HVT/LVT/RVT/SRAM)
• Read and linked synthesized gate-level netlist

2. Floorplan Generation

• Core utilization set to 70% for congestion-safe routing
• Aspect ratio fixed for balanced placement
• Defined site rows and core offsets for structured placement
• Saved initial floorplan checkpoint

3. Pin Placement Strategy

• Input/output pins placed on Metal Layer M5
• Clock pins with higher spacing and protection
• Data inputs with standard spacing
• Outputs with isolated placement rules

4. Multi-Voltage Integration

• Loaded and committed UPF power intent
• Created voltage-aware physical regions
• Verified multi-voltage correctness using check_mv_design
• Ensured correct separation of 0.75V and 0.95V domains at layout level

5. Power Grid Preparation

• Executed power planning script (powerplan.tcl)
• Established robust power delivery network (PDN) for multi-voltage domains

Skills Demonstrated

• Physical Design (ICC2)
• Floorplanning
• Pin Planning
• Multi-Voltage Integration
• UPF Commit Flow
• Power Grid Design
• Library Management (NDM)
• ASIC Backend Flow
• Early Stage Design Closure

Key Achievement

Built a complete physical design initialization flow that integrates multi-voltage power intent, structured floorplanning, pin strategy, and DFT readiness, forming a solid foundation for placement, routing, and timing closure of a silicon-ready cryptographic SoC.

Placement Preparation & Optimization

Developed a pre-placement and placement-optimization setup script for a multi-voltage cryptographic SoC using an ICC2-style physical design flow. This stage prepares the design for legalization, congestion control, and timing-aware placement while ensuring proper handling of macros, scan chains, and MCMM constraints.

Design Focus

The flow focuses on clean design state restoration, placement rule configuration, congestion control, and routing layer control before running full placement optimization.

Key Features

• Restores and initializes clean placement stage from verified design snapshot
• Applies MCMM timing constraints setup for multi-corner, multi-mode analysis
• Handles macro and fixed cell placement constraints
• Enables advanced legalization and placement repair algorithms
• Controls cell density and fanout limits for congestion prevention
• Configures routing layer restrictions for early design stability
• Prepares scan chain and DEF-based physical integration
• Ensures placement-ready environment for optimization flow

Flow Breakdown

1. Design Restoration & Initialization

• Restores design state from initial_placement
• Opens clean block for placement stage processing
• Runs pre-placement design checks

2. Placement Optimization Controls

• Enables advanced legalization engine
• Activates search-and-repair placement optimization
• Limits placement density to 0.75 for congestion control
• Restricts maximum fanout to 25 for signal integrity

3. Routing & Layer Management

• Defines ignored routing layers (M2–M6 restriction setup)
• Configures net routing rules
• Hard layer enforcement for critical nets
• Flexible pin connection handling for optimization

Skills Demonstrated

• Physical Design (ICC2/Innovus)
• Placement Optimization
• MCMM Integration
• Congestion Management
• Macro Handling
• Scan Integration
• Design Rule Awareness
• Routing Constraint Setup
• ASIC Backend Flow Preparation

Key Achievement

Established a robust placement-ready environment for a multi-voltage SoC, integrating MCMM timing constraints, scan chain structure, congestion control, and routing awareness to ensure smooth transition into full placement and optimization stages.

Clock Tree Synthesis (CTS)

Developed a complete Clock Tree Synthesis (CTS) execution script for a standard-cell-only, multi-voltage cryptographic SoC, focusing on clock distribution, skew control, and timing closure across multiple PVT corners. The flow integrates clock constraints, NDR rules, clock uncertainty management, and multi-voltage level shifting, ensuring robust and low-skew clock propagation.

Key Features

• Built a CTS flow excluding macros (standard-cell-only clock tree)
• Defined clock-specific routing rules (double width/spacing NDR)
• Applied multi-corner skew targets for SS/FF process conditions
• Configured clock uncertainty for setup and hold across all scenarios
• Enabled CRPR (Clock Reconvergence Pessimism Removal) for timing accuracy
• Inserted clock-domain level shifters for multi-voltage crossing
• Executed full clock build → route → optimization flow
• Performed final hold fixing and DFT-aware clock optimization

Flow Breakdown

1. Clock Routing Rules (NDR)

• Removes default routing constraints
• Defines double-width & double-spacing rules for clock nets
• Restricts clock routing between M4–M5 layers for stability
• Improves signal integrity and reduces clock noise

2. Clock Constraint Definition

• Sets max transition limits (0.15 ns)
• Defines target skew per corner:
  • SS corners → relaxed skew
  • FF corners → tighter skew (0.02)
• Enables corner-aware CTS optimization

3. CTS Execution Flow

• Build Clock Tree (generates initial balanced clock structure)
• Clock Routing (physically routes clock network)
• Saves intermediate CTS states

4. Final Optimization Stage

• Enables high-effort hold fixing
• DFT-aware scan clock optimization enabled
• Performs final timing and skew cleanup
• Produces signoff-ready clock network

Skills Demonstrated

• Clock Tree Synthesis (CTS)
• Multi-Voltage Clock Design
• NDR Routing Strategy
• Skew Optimization
• Clock Uncertainty Modeling
• CRPR
• ASIC Physical Design (ICC2/Innovus)
• Timing Closure
• Clock Distribution Architecture

Key Achievement

Designed a robust multi-voltage CTS flow with corner-aware skew control, clock-specific routing rules, and integrated level shifting, ensuring a low-skew, timing-clean clock network ready for full-chip signoff.

Routing & Signoff Optimization

Developed a full-chip production routing script for a multi-voltage cryptographic SoC, focusing on timing closure, congestion-aware routing, and signal integrity optimization. The flow is designed for signoff-quality routing, ensuring correct electrical behavior across all PVT corners and voltage domains.

Key Features

• Enabled timing-driven routing across global, track, and detail stages
• Integrated crosstalk-aware routing for signal integrity (SI) reduction
• Applied statistical SI analysis for accurate noise modeling
• Ensured clock network protection during routing
• Included antenna rule integration for fabrication compliance
• Performed routability checks before routing execution
• Executed full route_auto → route_opt → signoff optimization flow
• Maintained consistent instance naming for debug and traceability

Flow Breakdown

1. Pre-Routing Verification

• Runs pre-route design checks to ensure clean netlist state
• Generates routability report to detect congestion risks early

2. Timing-Driven Routing Strategy

• Enables timing optimization at all routing stages (Global, Track, Detail)
• Ensures critical paths are prioritized during physical wire placement

3. Signal Integrity (SI) Optimization

• Enables crosstalk-aware routing engine
• Uses statistical aggregation model for SI accuracy
• Improves noise robustness in high-speed nets

4. Routing Execution Flow

• Global routing
• Track assignment
• Detailed routing
• Saves checkpoints at each stage for debug and recovery

5. Final Optimization

• Runs post-route optimization (route_opt)
• Fixes timing violations and improves wire quality
• Produces signoff-ready routed design

Skills Demonstrated

• Physical Design Routing
• Timing-Driven Routing
• Crosstalk Analysis (SI)
• Antenna Rule Compliance
• Congestion Management
• ICC2/Innovus Routing Flow
• Clock Network Protection
• ASIC Signoff Methodology

Key Achievement

Implemented a signoff-grade routing flow for a multi-voltage cryptographic SoC, integrating timing, SI, and manufacturability constraints to achieve a robust, fabrication-ready routed design with improved performance and reliability.

Signoff Extraction & PrimeTime Handoff

Developed a signoff-stage timing closure and extraction flow for a multi-voltage cryptographic SoC, focusing on accurate parasitic extraction (StarRC) integration and PrimeTime STA handoff setup. This stage ensures that post-route parasitics, power intent, and timing constraints are correctly prepared for final timing signoff analysis.

Flow Purpose

The flow bridges physical design signoff data → extraction (SPEF/NXTGRD) → static timing analysis (PrimeTime), enabling accurate silicon-level timing verification.

Key Features

• Integrated signoff parasitic extraction flow using StarRC
• Managed corner-based parasitic models (Cbest / Cworst scenarios)
• Generated accurate SPEF for post-route timing analysis
• Prepared PrimeTime-ready netlist and constraint setup
• Configured multi-corner SDC generation (FF / SS scenarios)
• Handled UPF integration for multi-voltage consistency
• Enabled coupling-aware parasitic analysis for SI accuracy
• Established clean handoff from physical design to STA signoff tools

Flow Breakdown

1. Parasitic Extraction (StarRC Stage)

Inputs used:

• Routed DEF
• NDM database
• Technology MAP files
• NXTGRD corner models

Generated parasitic outputs:

• Cbest SPEF (fast corner)
• Cworst SPEF (slow corner)

2. SPEF Integration for STA

• Extracted SPEF files copied into PrimeTime input environment
• Ensures consistency between physical and timing domains
• Enables multi-corner STA setup

3. Netlist & Constraint Preparation

• Generated optimized post-route netlist (routed_netlist.v)
• Exported scenario-based SDCs (ff_125c.sdc, ss_125c.sdc)
• Ensures MCMM-aware timing analysis in PrimeTime

Skills Demonstrated

• Static Timing Analysis (PrimeTime)
• Parasitic Extraction (StarRC)
• SPEF Generation
• MCMM Signoff Flow
• Multi-Voltage STA
• Power Intent Integration (UPF)
• Crosstalk-Aware Timing
• ASIC Signoff Methodology

Key Achievement

Built a complete signoff extraction-to-STA handoff flow, enabling accurate post-route timing analysis using real parasitics (SPEF/NXTGRD) and multi-corner constraints, ensuring silicon-accurate verification of a multi-voltage cryptographic SoC.

DRV Fixes - Max Transition & Capacitance ECO

1. Automated Cell Upsizing Script

Developed an ECO (Engineering Change Order) automation script to fix max transition and capacitance violations in a multi-voltage ASIC design. The script analyzes timing violation reports, identifies critical nets, and automatically upsizes driving cells to improve signal strength and meet timing constraints.

Upsizing Features

• Parses max transition violation reports automatically
• Extracts critical net names causing timing violations
• Identifies driver cells from output pins of affected nets
• Dynamically selects next higher drive strength from standard cell library
• Performs automatic cell resizing (upsizing)
• Applies incremental placement legalization after ECO changes
• Updates timing analysis after each modification
• Handles errors gracefully using TCL catch mechanism
• Tracks success/failure of each ECO operation

Upsizing Flow Breakdown

1. Violation-Driven Net Extraction

• Reads timing report file (max_trans_vio.txt)
• Filters valid net entries from report
• Ignores headers and metadata lines

2. Drive Strength Optimization

• Parses library naming convention (e.g., AND2X1_HVT)
• Extracts current drive strength
• Computes next higher strength version
• Constructs target library cell name

3. Cell Upsizing (ECO Fix)

• Replaces driver cell with higher strength version
• Improves transition time and load driving capability
• Improves timing slack

2. Automated Buffer Insertion Script

Developed an ECO automation script for fixing max capacitance violations in a multi-voltage ASIC design by inserting buffers on critical nets. The flow parses violation reports, identifies problematic nets, and strategically inserts buffering cells close to driver pins to reduce load and improve signal integrity.

Buffer Insertion Features

• Parses max capacitance violation report automatically
• Extracts critical violating net names
• Identifies driver output pins for each net
• Inserts high-drive buffer cells (NBUFFX8_LVT)
• Positions buffers near driver pin location for optimal timing impact
• Performs incremental placement legalization after insertion
• Handles failures using robust TCL error catching
• Provides success/failure statistics for ECO debugging

Buffer Insertion Flow Breakdown

1. Violation Report Processing

• Reads max_cap_vio.txt
• Filters valid violation entries
• Extracts net names from report columns

2. Buffer Insertion Strategy

• Inserts buffer cell (NBUFFX8_LVT)
• Uses insert_buffer command on driver pin
• Reduces capacitive load seen by original driver
• Improves signal integrity and transition delay

3. Incremental Legalization

• Runs legalize_placement -incremental
• Fixes placement overlaps introduced by buffer insertion
• Maintains design legality without full re-place

Skills Demonstrated

• Physical Design ECO
• Buffer Insertion Strategy
• Max Capacitance Fixing
• Signal Integrity Optimization
• TCL Automation
• Incremental Placement
• Timing Closure Techniques
• ASIC Physical Design Debugging

Key Achievement

Built an automated ECO buffer insertion flow that intelligently resolves max capacitance violations by inserting optimized buffer cells near driver pins, enabling fast, localized timing and SI fixes in late-stage ASIC physical design.

Setup Fixes - Voltage Area & Floorplan Optimization

This section covers advanced physical design optimization techniques for multi-voltage ASIC implementation, including automated voltage-area generation and floorplan iteration cycles.

Voltage Area Creation Script

Developed a dynamic voltage-area creation script for a multi-voltage cryptographic SoC, focusing on automatic calculation and generation of low-power domain (PD_LP) placement regions based on cell area utilization and physical design constraints.

Voltage Area Features

• Automatically calculates total area of low-power key generation block (u_key_gen_lp)
• Applies target utilization (80%) for voltage area sizing
• Dynamically computes height and width based on standard cell grid alignment
• Rounds dimensions to technology-compliant placement grid
• Generates voltage-area coordinates with guard-band isolation
• Defines physical region for PD_LP power domain
• Removes previous voltage regions before regeneration for consistency

Voltage Area Flow Breakdown

1. Area Extraction & Calculation

• Extracts area of all cells in low-power block
• Accumulates total design area dynamically
• Computes effective voltage-area requirement using utilization factor (0.8)

2. Voltage Area Sizing

• Converts logical area → physical region size
• Calculates height (grid-aligned rounding)
• Calculates width (derived from area/height ratio)
• Ensures compatibility with placement site grid

3. Grid-Aware Physical Adjustment

• Rounds dimensions to height grid: 1.672
• Rounds dimensions to width grid: 0.152
• Prevents placement and legalization violations

4. Region Definition & Guard Bands

• Defines origin point (llx, lly)
• Computes opposite corner (urx, ury)
• Creates bounding box for voltage area
• Applies guard band spacing (5.016 units) to isolate domain

Skills Demonstrated (Voltage Area)

• Voltage-Aware Floorplanning
• Physical Design Automation
• Area Estimation
• Multi-Voltage Partitioning
• TCL Scripting for PD
• Grid-Constrained Layout Design
• Power Domain Isolation
• ASIC Physical Design Methodology

Key Achievement (Voltage Area)

Built an automated voltage-area generation methodology that dynamically sizes and places a low-power domain region based on real cell area and utilization constraints, ensuring accurate, grid-aligned, and isolation-safe multi-voltage floorplanning for ASIC implementation.

Floorplan Iteration & Congestion Fix

This section shows a real physical design floorplan optimization cycle, where an initial high-utilization "Y-shaped" floorplan caused severe routing congestion, and then was corrected by resizing and rebalancing the core area.

Initial Floorplan Problem

The first floorplan used a Y-shaped boundary, which created uneven routing resources and congestion hotspots.

Problem Analysis

• Core utilization: ~84.75% (too high for routing)
• Severe routing congestion: ~70%
• Total overflow: 377,057
• High congestion GRCs: 69.13%
• Horizontal routing overflow: 81.91% (critical bottleneck)
• Vertical routing overflow: 56.36%

Root Cause Analysis

• High utilization left insufficient routing whitespace
• Irregular "Y-shape" created uneven routing channels
• Horizontal congestion was especially severe
• Placement had no room for detours or detangling nets

Fix Strategy

The floorplan was re-initialized with improved geometry and reduced density.

Key Changes

• Expanded and reshaped boundary for better routing flow
• Reduced core utilization from ~84.75% to ~76.71%
• Improved routing channel distribution
• Preserved Y-shape structure but made it more routing-friendly

Final Outcome

• Core utilization reduced to 76.71% (safe range)
• Improved routing feasibility
• Significantly lower congestion risk

Engineering Insight

High utilization + irregular floorplan shapes = routing congestion explosion

Even if placement fits, routing will fail without proper whitespace planning.

Skills Demonstrated

• Floorplanning Optimization
• Congestion Analysis
• Utilization Tuning
• Routing Channel Design
• Physical Design Debugging
• ICC2/Innovus Flow
• Iterative Floorplan Refinement

Key Achievement

Identified and fixed a severe floorplan-induced routing congestion issue by iteratively refining a Y-shaped floorplan, reducing utilization and improving routing resources, resulting in a clean, routable, and physically balanced chip layout.

Floorplan Initialization – A Shape

This step initializes the chip floorplan for the multi-voltage cryptographic SoC by defining the core area, boundary shape, site rows, and routing tracks. It forms the foundation for all later physical design stages like placement, power planning, CTS, and routing.

Core Concept

The command defines a custom, non-rectangular floorplan boundary, which allows flexible chip shaping instead of a simple rectangular die. This is useful for realistic ASIC designs where IOs, macros, or power regions may require irregular boundaries.

What This Flow Does

1. Clears Existing Floorplan

• Removes any previously created floorplan objects
• Ensures a clean restart of physical design setup

2. Defines Chip Boundary

The boundary is defined as a polygon with coordinates that create a custom stepped floorplan shape, instead of a simple rectangle.

3. Core Creation

• Core region is generated inside the boundary
• Core utilization = ~80.32%
• Ensures balance between area efficiency and routing congestion margin

4. Site Array Generation

• Standard-cell rows (site rows) are created
• Cells will be placed aligned to these rows
• Floorplan snaps to manufacturing-compatible grid

5. Routing Track Setup

• Routing tracks are automatically generated
• Enables uniform routing resources across the chip
• Prepares design for congestion-aware placement and routing

6. Core Alignment Fix

• Core boundary snaps to site grid
• Ensures legality for standard cell placement
• Prevents placement misalignment issues later

Why This Step Matters

This is the base physical structure of the chip, and it directly impacts:

• Placement quality
• Congestion behavior
• Timing closure
• Power grid quality
• Routing efficiency

A poorly defined floorplan here can break the entire backend flow.

Skills Demonstrated

• Physical Design Floorplanning
• Core/Die Definition
• Site Row Generation
• Routing Track Setup
• ASIC Layout Planning
• Utilization Planning
• PnR Initialization Flow

Key Achievement

Defined a custom polygon-based floorplan with controlled utilization and proper site alignment, forming a silicon-ready physical foundation for a multi-voltage cryptographic SoC.

Floorplan Iteration – Y-Shape Congestion Fix

This section shows a real physical design floorplan optimization cycle, where an initial high-utilization "Y-shaped" floorplan caused severe routing congestion, and then was corrected by resizing and rebalancing the core area.

Initial Floorplan (Problem Case)

The first floorplan used a Y-shaped boundary, which created uneven routing resources and congestion hotspots.

Key Observations (Problem Phase)

• Core utilization: ~84.75% (too high for routing)
• Severe routing congestion: ~70%

Congestion Report Summary (Before Fix)

• Total overflow: 377,057
• High congestion GRCs: 69.13%
• Horizontal routing overflow: 81.91% (critical bottleneck)
• Vertical routing overflow: 56.36%

Problem Root Cause

• High utilization left insufficient routing whitespace
• Irregular "Y-shape" created uneven routing channels
• Horizontal congestion was especially severe
• Placement had no room for detours or detangling nets

Fix Strategy (Floorplan Rework)

The floorplan was re-initialized with improved geometry and reduced density.

Key Changes

• Expanded and reshaped boundary for better routing flow
• Reduced core utilization from ~84.75% → ~76.71%
• Improved routing channel distribution
• Preserved Y-shape structure but made it more routing-friendly

Updated Floorplan (After Fix)

Improvements (After Fix)

• More balanced area distribution
• Increased whitespace for routing escape paths
• Reduced congestion pressure significantly
• Better alignment with site rows and routing tracks

Final Outcome

• Core utilization reduced → 76.71% (safe range)
• Improved routing feasibility
• Significantly lower congestion risk

Engineering Insight

High utilization + irregular floorplan shapes = routing congestion explosion

Even if placement fits, routing will fail without proper whitespace planning.

Skills Demonstrated

• Floorplanning Optimization
• Congestion Analysis
• Utilization Tuning
• Routing Channel Design
• Physical Design Debugging
• ICC2/Innovus Flow
• Iterative Floorplan Refinement

Key Achievement

Identified and fixed a severe floorplan-induced routing congestion issue by iteratively refining a Y-shaped floorplan, reducing utilization and improving routing resources, resulting in a clean, routable, and physically balanced chip layout.

MCMM Constraints - Multi-Corner Multi-Mode

MCMM (Multi-Corner Multi-Mode) timing analysis is critical for ensuring robust physical design closure across multiple operating conditions. This section provides comprehensive details on the MCMM setup and constraint methodology used in the crypto_top project.

MCMM Overview

Multi-Corner Multi-Mode analysis ensures that the design meets timing requirements across:

• Process Corners: FF (Fast-Fast) and SS (Slow-Slow)
• Temperature Conditions: -40°C and 125°C
• Operating Modes: Functional and Scan/Test
• Voltage Domains: 0.95V and 0.75V

Corner Specifications

Operating Modes

Functional Mode

• Normal operational mode
• Encryption/decryption operations
• Core cryptographic functions active

Scan/Test Mode

• Test/Debug operational mode
• Scan chain enabled
• Different timing characteristics due to scan path

MCMM Analysis Benefits

• Comprehensive timing coverage across all operating conditions
• Detects timing failures that single-corner analysis might miss
• Ensures hold time compliance in best-case conditions
• Ensures setup time compliance in worst-case conditions
• Enables efficient multi-voltage timing closure
• Reduces silicon failure risk and improves reliability

Constraint Management in Physical Design

During physical design stages (placement, CTS, routing), MCMM constraints guide:

• Placement Optimization: Cell placement to minimize critical path delays
• Clock Tree Synthesis: Clock skew control across all corners
• Routing: Wire routing prioritizing critical timing paths
• Signoff Analysis: Final timing verification across all scenarios

Manual & Documentation

Comprehensive documentation for the Multi-Voltage Crypto Core project is available in multiple formats to support different learning and reference preferences.

Available Resources

Manual Contents

Both manual formats include:

• Project overview and objectives
• Multi-voltage architecture explanation
• RTL design details and code walkthroughs
• UPF power intent specification guide
• Timing constraint development (SDC and MCMM)
• Synthesis flow and DFT insertion techniques
• Physical design implementation (floorplanning, placement, CTS, routing)
• Power planning and PDN design methodology
• Signoff and timing closure strategies
• ECO (Engineering Change Order) techniques
• Troubleshooting and optimization tips
• Tool command references and examples

Documentation Navigation Tips

• For First-Time Users: Start with the project overview and architecture sections
• For RTL Engineers: Focus on RTL design and UPF specification sections
• For Physical Design Engineers: Reference floorplanning through signoff sections
• For Flow Automation: Review TCL script sections and tool command references
• For Troubleshooting: Consult the physical design debugging and ECO sections

Extra Files & Resources

Additional documentation, templates, and reference materials for the Multi-Voltage Crypto Core project.

Coming Soon

Additional resources are being prepared and will be made available soon. This section will include:

• Technology reference files and LEF/DEF templates
• Tool configuration files and setup scripts
• Design checklist and verification templates
• Performance benchmarking data and reports
• FAQs and troubleshooting guides
• Additional case studies and examples
• Video tutorials and workflow demonstrations

Project Repository

For the complete and latest resources, visit the official GitHub repository: